1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method for manufacturing the same, and more specifically to a semiconductor integrated circuit called a "BiMOS" or "BiCMOS" in which bipolar transistors and MOS transistors are formed on the same single semiconductor substrate, and a method for manufacturing the same.
2. Description of Related Art
One problem in microminiaturizing MOS transistors is the hot carrier effect. This is caused because when channel length is shortened, the electric field in proximity of the drain becomes strong. Namely, electrons accelerated by the high electric field collide against the silicon crystal to generate electron-hole pairs, so that the electrons thus generated are trapped in gate oxide film, with the result that the film quality of the gate oxide film is deteriorated. In order to suppress this hot carrier effect, it is known that it is effective to adopt a so called LDD (lightly doped drain) structure in which a low impurity concentration region is provided at an end of the drain. At present, this structure is widely used.
On the other hand, in order to realize a high speed operation and a high performance in the MOS semiconductor integrated circuit, the BiMOS or BiCMOS technology has been adopted in which bipolar transistors and MOS transistors are formed mixedly on the same single semiconductor substrate. By adopting the BiMOS technology, it is possible to obtain together high integration density of the MOS integrated circuit and high speed operation of the bipolar transistors. Furthermore, by using BiCMOS technology, it is possible to realize a semiconductor integrated circuit which simultaneously satisfies the need for low consumed current of the CMOS circuit and high speed operation of the bipolar transistors.
One example of the prior art technology for forming MOS transistors of the LDD structure and bipolar transistors on the same single semiconductor substrate, is disclosed by Japanese Patent Application Laid-open Publication No. JP-A-02-237146. Now, this prior art process will be described with reference to FIGS. 1 to 3.
FIG. 1 illustrates a substrate in a condition just before a gate electrode of MOS transistors is formed in the process of manufacturing the BiCMOS semiconductor integrated circuit. In this example, an nMOS transistor is formed in an area A, and a pMOS transistor is formed in an area B. A bipolar transistor is formed in an area C. An area D is a device isolation part for isolating the pMOS transistor and the bipolar transistor from each other.
First, N-type buried layers 302 are formed by ion-implanting arsenic to a P-type silicon substrate 301 in the areas B and C, and a P-type buried layer 303 is formed by ion-implanting boron to the P-type silicon substrate 301 in the area A and D. Then, an N-type epitaxial layer 304 is grown on the whole surface of the substrate.
By ion-implanting boron to the N-type epitaxial layer 304 in the areas A and D, P-type wells 305 are formed, and by ion-implanting phosphorus to the N-type epitaxial layer 304 in area B, an N-type well 306 is formed. Furthermore, a field oxide film 307 is formed on a surface of the substrate, and then, after an ion implantation for controlling the threshold V.sub.T and an ion implantation for forming an intrinsic base region 309 for the bipolar transistor are carried out, a gate oxide film 310 is formed.
Thereafter, as shown in FIG. 2, a polysilicon is deposited as a gate electrode material, and selectively etched to form gate electrodes. Here, gate electrodes 312a and 312b are formed in areas A and B, but in area C, a polysilicon film 312c is left above the intrinsic base region 309. Then, by ion-implanting phosphorus at a low concentration in area A, LDD N.sup.- regions 314 are formed, and by ion-implanting boron at a low concentration in the area B, LDD P.sup.- regions 315 are formed. Furthermore, an oxide silicon film is grown on whole surface, and then, an isotropic etching is carried out to form side walls 316.
Thereafter, the gate oxide film 310 and the polysilicon film 312c remaining above the intrinsic base region 309 in area C are selectively removed. Then, a mask is formed of a photo resist, and by ion-implanting arsenic in areas A and C, N.sup.+ source/drain regions 319 of the nMOS transistor and an emitter diffused region 313 are formed as shown in FIG. 3. Similarly, after a photo resist mask is formed, by ion-implanting boron fluoride in areas B and C, P.sup.+ source/drain regions 317 of the pMOS transistor and an graft base region 318 are formed as shown in FIG. 3. Finally, an interlayer insulator film 320 is deposited and planarized, and then, contact holes are formed and electrode wirings 321 are formed of aluminum. Thus, the BiCMOS semiconductor device having the sectional structure shown in FIG. 3 is obtained.
In the above mentioned manufacturing process, when the anisotropic etching for forming the side wall spacers is carried out, area C of the bipolar transistor is covered with the gate oxide film 310 and the polysilicon film 312c. Therefore, an area in which an emitter-base junction is formed in future, is protected from damage resulting from the anisotropic etching.
In generally, when the emitter-base junction of the bipolar transistor is damaged, recombination centers generated by the damage will increase recombination current in the forward direction of the bipolar transistor and lower an emitter injection coefficient, with the result that the current amplification factor (h.sub.FE) in the low current region drops. Therefore, the above mentioned prior art manufacturing process can produce a bipolar transistor having excellent characteristics.
There is another prior art manufacturing process of forming the graft base and the emitter diffused region by utilizing the polysilicon electrode. Now, the second prior art manufacturing process will be described with reference to FIGS. 4 to 6. In FIGS. 4 to 6, elements corresponding to those shown in FIGS. 1 to 3 are given the Reference Numerals having the same two least significant digits as those of Reference Numerals given to the corresponding ones shown in FIGS. 1 to 3, and explanation thereof will be omitted.
As shown in FIG. 4, after a intrinsic base region 409 is formed by ion-implanting boron into a base region, a silicon oxide film 427 is formed to previously cover a portion in which an emitter diffused region will be formed in a later manufacturing step, and then, a polysilicon for forming the base electrode is grown, and boron fluoride is ion-implanted so as to form a graft base region 418. Thereafter, the polysilicon is patterned to form a base electrode 428, and then, an interlayer insulator film 429 is grown.
Then, as shown in FIG. 5, the interlayer insulator film in areas A and B is selectively etched to the substrate surface, and a gate oxide film 410 and a gate electrode polysilicon are grown, and the polysilicon is patterned to form gate electrodes 412a and 412b. Furthermore, in like manner to the first prior art manufacturing process, phosphorus is ion-implanted in area A so as to form LDD N.sup.- region 419, and boron is ion-implanted in area B so as to form LDD P.sup.- region 415.
Thereafter, an oxide film for forming a side wall spacer for the MOS transistor is grown, and an anisotropic etching is performed so as to form a side wall 416. Furthermore, a selective ion-implantation is performed in area A and in area B, respectively, so as to form N.sup.+ source/drain regions 419 and P.sup.+ source/drain regions 417, respectively.
Thereafter, as shown in FIG. 6, after an interlayer insulator film 422 is grown, the interlayer insulator film 422 and the base electrode 428 are selectively etched to form an emitter opening. Furthermore, with a well-known self-alignment contact forming technology, an emitter region is formed. Namely, after the emitter opening is formed, for example, a silicon oxide film is formed, and then, an anisotropic etching is performed so as to form a side wall 425 within the emitter opening. Furthermore, an emitter electrode forming polysilicon is grown, and an emitter diffused region 412 is formed by ion-implanting arsenic. Thereafter, the polysilicon is patterned to form an emitter electrode 426. Finally, an interlayer insulating film 420 is grown and a heat treatment is carried out to planarize the surface. Necessary contact holes are formed, and electrode wiring 421 formed of aluminum is deposited. Thus, the BiCMOS semiconductor device having the sectional structure shown in FIG. 3 is obtained.
In this second prior art manufacturing process, since the emitter region is formed through the emitter electrode forming polysilicon, differently from the first prior art manufacturing process, it is possible to form the emitter-base junction shallowly, near to the surface of the substrate. Accordingly, it is possible to form a bipolar transistor having even more excellent performance.
However, in the first prior art manufacturing process, before the bipolar transistor is formed, the polysilicon film covered on the intrinsic base region has to be removed by the selective etching after forming a photo resist mask. Therefore, the manufacturing process is complicated, and the manufacturing cost is high.
In the second prior art manufacturing process, on the other hand, the process required for forming the MOS transistor and the process required for forming the bipolar transistor exist independently of each other. Therefore, the manufacturing process is complicated similarly to the first prior art manufacturing process, and the manufacturing cost is high.